library verilog;
use verilog.vl_types.all;
entity exp3 is
    port(
        mode_choose     : in     vl_logic_vector(7 downto 0);
        input_data      : in     vl_logic_vector(7 downto 0);
        clk             : in     vl_logic;
        button_hang     : in     vl_logic_vector(3 downto 0);
        button_lie      : out    vl_logic_vector(3 downto 0);
        wei_xuan        : out    vl_logic_vector(5 downto 0);
        duan_xuan       : out    vl_logic_vector(7 downto 0)
    );
end exp3;
